PLL circuits are used in various fields, and various semiconductor integrated circuits having the PLL circuit are known. Characteristics of the PLL include a lock-up time, a jitter characteristic, a phase noise characteristic and the like, and the PLL circuit is designed so that the PLL performs a stable operation.
FIG. 1 is a diagram illustrating an example of a conventional PLL circuit. A PLL circuit 1 includes a Phase Frequency Detector (PFD) 2, a Charge Pump (CP) 3, a Low-Pass Filter (LPF) 4, a Voltage Controlled Oscillator (VCO) 5, and a frequency divider (DIV) 6 which are coupled as illustrated in FIG. 1.
However, when the PLL circuit 1 is fabricated by a semiconductor process such as a Complementary Metal Oxide Semiconductor (CMOS) process, a variance is generated in the characteristics of the elements forming each part of the PLL circuit 1 due to inconsistencies introduced during the fabrication process. For this reason, parameters including an output current ICP of the CP 3, a resistance RLPF of a resistor RLPF within the LPF 4, capacitances CLPF and CP of capacitors CLPF and CP within the LPF 4, and a VCO gain KVCO of the VCO 5 become larger or smaller than the respective designed values. As a result, a variance is generated in the characteristics of the PLL among the individual PLL circuits 1.
FIGS. 2 and 3 are diagrams illustrating a state where the variance is generated in the characteristics of the PLL. FIG. 2 illustrates a gain versus frequency characteristic of the PLL circuit 1, and FIG. 3 illustrates a phase delay versus frequency characteristic of the PLL circuit 1. In FIGS. 2 and 3, a solid line indicates the characteristic for a case where all of the parameters have the designed value, and a dotted line indicates the characteristic for a case where the variance is generated in at least one of the parameters and the at least one of the parameters is larger or smaller than the corresponding designed value. In FIG. 2, the ordinate and the abscissa are indicated in arbitrary logarithmic units.
The frequency at which the gain becomes 0 db and the phase margin greatly affect the stability of the PLL, and may be determined from the following three parameters ω1, ω2 and ω3. The phase margin corresponds to a difference of the phase delay at the frequency which makes the gain 0 dB from −180°. In the following formulas, Ndiv denotes a multiplication factor of the frequency divider 6, and Call denotes a capacitance represented by Call=CLPF+CP.ω1={KVCO·ICP/2π·Ndiv·Call}1/2 ω2=1/(RLPF·CLPF)ω3=1/(RLPF·CP)
FIGS. 4 and 5 are diagrams for explaining the three parameters ω1, ω2 and ω3. A solid line in FIG. 4 indicates a gain versus frequency characteristic of the PLL circuit 1, and a solid line in FIG. 5 indicates a phase delay versus frequency characteristic of the PLL circuit 1. In addition, in FIGS. 4 and 5, dotted lines indicate the parameters ω1, ω2 and ω3 at the frequency which makes the gain 0 dB. In FIG. 4, the ordinate and the abscissa are indicated in arbitrary logarithmic units.
For example, a Japanese Laid-Open Patent Publication No. 2006-33108 proposes a semiconductor integrated circuit in which a large variance in the characteristics of the PLL will not be generated even if the parameters vary. This proposed semiconductor integrated circuit includes a control part, a charge pump, and a LPF. The control part outputs an amount of data depending on a product of a resistance of a resistor part and a capacitance of a capacitor part. The charge pump has a structure such that an output current value thereof depends on a resistance of a portion made up of resistors that are coupled in parallel, and the resistance of the part made up of the resistors is reduced by increasing the number of resistors coupled in parallel depending on the amount of data. The LPF has a structure such that the resistance of a part made up of resistors that are coupled in parallel is reduced by increasing the number of resistors coupled in parallel depending on the amount of data. In other words, the parameter ω1 reduces the effects of the variance in the resistances of the resistors and the capacitances of the capacitors within the charge pump, and the parameters ω2 and ω3 reduce the effects of the variance in the resistances of the resistors and the capacitances of the capacitors within the LPF.
Accordingly, in the proposed semiconductor integrated circuit described above, the parameters ICP and Call which determine the parameter ω1, the parameters RLPF and CLPF which determine the parameter ω2, and the parameters RLPF and CP which determine the parameter ω3 in the above described formulas of the three parameters ω1, ω2 and ω3 are less affected by the inconsistencies introduced during the fabrication process. Hence, the variance in the characteristics of the PLL caused by the inconsistencies introduced during the fabrication process can be suppressed to a certain extent by the proposed semiconductor integrated circuit.
In the proposed semiconductor integrated circuit, if the parameter RLPF has a resistance that is 3/2 times that of the corresponding designed value, for example, the parameter ω2 can be corrected to the corresponding designed value by correcting the parameter CLPF to a capacitance that is ⅔ times that of the corresponding designed value. However, the variance in the capacitance also affects the parameter ω1, and thus, there is a limit to correcting the variance in the characteristics of the PLL by such a variance correction method. For example, in an extremely large-scale CMOS process, the variance is also generated in the transistor characteristics, and the VCO gain KVCO and the like are greatly affected thereby. However, the proposed semiconductor integrated circuit does not take into consideration such a large variance in the VCO gain KVCO and the like, and for this reason, the parameter ω1 greatly varies when the VCO gain KVCO and the like greatly vary.
Therefore, the parameters ω1, ω2 and ω3 are not comprehensively corrected according to the conventional variance correction method, and the variance in the characteristics of the PLL cannot be corrected with a high accuracy.